- J. A. Davis, D. Brown, W. Henderson, “ Fractal Electrode Formation in Metal-Insulator Composites Near the Percolation Threshold,”
*IEEE Transactions on Nanotechnology*, vol. 12, no. 5, pp. 725-733, Sept. 2013. - G. Lopez, J. Davis, and J. Meindl, “A New Physical Model and Experimental Measurements of Copper Interconnect Resistivity Considering Size Effects and Line-Edge Roughness (LER),”
*Proceedings of the IEEE 2009 International Interconnect Technology Conference (IITC)*, pp. 231-234, June 2009. - M. Usselman, J. Davis, and J. Rosen, “Diversifying Participation in FIRST LEGO League,”
*2008 American Society for Engineering Education (ASEE) Conference Proceedings*, pp. 750, 2008. - V. Deodhar and J.A. Davis, “Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Application, vol. 55, no. 4, pp.1023-30, May 2008.
- D. Sekar, A. Naeemi, R. Sarvari, J. Davis, and J. Meindl, “Intsim: A CAD Tool for Optimization of Multilevel Interconnect Networks,”
*Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)*, pp. 560-567, November 2007. - A. Joshi, G. Lopez, and J.A. Davis, “Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing,”
*IEEE Transactions on VLSI Systems*, vol. 15, no. 9, pp. 990-1002, September 2007. - D. Sekar, B. Dang, J.A. Davis, J.D. Meindl, “Electromigration Resistant Power Delivery Systems,” IEEE Electron Device Letters, Vol. 28, no. 8, pp. 767-769, August 2007.
- H. Yamamoto and J.A. Davis, “Decreased Effectiveness on On-chip Decoupling Capacitance in High Frequency Operation,”
*IEEE Transactions on VLSI Systems,*vol. 15, no. 6, pp. 649-659, June 2007. - G. Lopez, R. Murali, R. Sarvari, K. Bowman, J. Davis, and J. Meindl, “The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors,”
*Proceedings of the IEEE 2007 International Interconnect Technology Conference*, pp. 40-42, June 2007. - P. Anbalagan and J.A. Davis, “A Priori Prediction of Tightly Clustered Connections Based on Heuristic Classification Trees,”
*Proceedings of the International Workshop on System Level Interconnect Prediction (SLIP)*, pp. 9-15, April 2006. - A. Joshi, V. Deodhar, and J. Davis, “Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing,”
*IEEE VLSI Design Conference*, pp. 773-776, January 2006. - D.C. Sekar, R. Venkatesan, K.A. Bowman, A. Joshi, J.A. Davis, and J.D. Meindl, “Optimal Repeaters for Sub-50nm Interconnect Networks,”
*Proceedings of the IEEE 2006 International Interconnect Technology Conference*, pp. 3-7, June 2006. - A. Joshi and J.A. Davis, “Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI),”
*IEEE Transactions on VLSI Systems*, vol. 13, no. 8, pp. 899-910, August 2005. - J.A. Davis, V. Deodhar, and A. Joshi, “The Impact of Wave Pipelining on Future Interconnect Technologies,”
*Advanced Metallization Conference 2005*, pp. 17-23, October, 2005. - A. Joshi and J. Davis, “Gigascale ASIC/SOC Design Using Wave-Pipelined Multiplexed (WPM) Routing,”
*Proceedings of the IEEE System-on-Chip Conference (SOCC)*, pp. 137-142, September 2005. - V. Deodhar and J. Davis, “Designing for Signal Integrity in Wave-Pipelined SoC Global Interconnects,”
*Proceedings of the IEEE System-on-Chip Conference (SOCC)*, pp. 207-210, September 2005. - V. Deodhar and J.A. Davis, “Optimization of Throughput Performance for Low Power VLSI Interconnects,”
*IEEE Transactions on VLSI Systems*, vol. 13, no. 3, pp. 308-318, March 2005. - V. Deodhar and J. Davis, “Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits,”
*IEEE International Symposium on Quality Electronic Design (ISQED)*, pp. 592-596, March 2005. - A. Naeemi, J. A. Davis, and J. D. Meindl, “Compact physical models for multilevel interconnect crosstalk in GSI,”
*IEEE Trans. Electron. Devices*, vol. 51, no. 11, pp. 1902-1912, November 2004. - A. Naeemi, J. A. Davis, and J. D. Meindl, “Analysis and Optimization of Co-planar RLC Lines for GSI global interconnection,”
*IEEE Trans. Electron. Devices*, vol. 51, pp. 985-995, June 2004. - A. Joshi and J.A. Davis, ” A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI)”
*2004 IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP)*, Paris, France, pp. 64-46, February 2004. - P. Anbalagan and J.A. Davis, “Maximum Multiplicity Distribution for Length Prediction Driven Placement,”
*17th International Conference on VLSI Design*, Mumbai, India, pp. 981-986, April 2004. - H. Luman and J.A. Davis, “Inductance Enhancement in Global Clock Distribution Networks,”
*2004 IEEE International Interconnect Technology Conference (IITC)*, San Francisco, CA, pp. 119-122, June 2004. - K.K. Ryu, A. Talpasanu, V. Mooney, and J.A. Davis, “Interconnect Delay Aware RTL Verilog Bus Architecture Generation for an SoC,”
*Asia-Pacific Conference on Advanced Systems Integrated Circuits (AP-ASIC 2004)*, Japan, pp.176-179, August 2004. - A. Naeemi, J.A. Davis, J.D. Meindl, “Compact Physical Models for Multielvel Interconnect Crosstalk in Gigascale SoC,”
*Proceedings of the IEEE International SoC Conference*, Rochester, NY, pp. 199-202, September 2003. - R. Venkatesan, J.A. Davis, and J.D. Meindl, “Optimal Multilevel Interconnect Architecture Aspect Ratios for GSOCs,”
*Proceedings of the 2003 IEEE SOC Conference*, Rochester, NY, pp. 17-20, September 2003. - R. Venkatesan, J.A. Davis, and J.D. Meindl, “Compact Distributed RLC Interconnect Models – Part IV: Unified Models for Time Delay, Crosstalk and Repeater Insertion,”
*IEEE Transactions on Electron Devices*, vol. 50, no. 4, pp. 1094-1102, April 2003. - V. Deodhar and J.A. Davis, “Voltage Scaling and Repeater Insertion for High-Throughput Low-Power Interconnect Networks,”
*Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (ISCAS)*, Bangkok, Thailand, pp. 349-352, June 2003. - R. Venkatesan, J.A. Davis, and J.D. Meindl, “Compact Distributed RLC Interconnect Models – Part III: Transients in Single and Coupled Lines with Capacitive Load Termination,”
*IEEE Transactions on Electron Devices*, vol. 50, no. 4, pp. 1081-1093, April 2003. - P. Anbalagan and J.A. Davis, “Maximum Multiplicity Distributions (MMD),”
*International Workshop on System Level Interconnect Prediction*, Monterey, CA, pp. 107-113, April 2003. - A. Talpasanu, G. Milford, K. S. A. Miles, and J.A. Davis “Computer Educational Datapath (CED): Basic Computer Design for K-12 Education,”
*IEEE International Conference on Information Technology (ITCC)*, Las Vegas, Nevada, pp. 86-90, April 2003. - J.W. Joyner, R. Venkatesan, J.A. Davis, J.D. Meindl, “The limits of system improvements through liquid diagonal routing of interconnects,”
*Proceedings of the IEEE 2003 International Interconnect Technology Conference*, June 2003, pp.227-229. - A. Naeemi, J.A. Davis, and J.D. Meindl, “Optimal Global Interconnect Devices for GSI,”
*Technical Digest of International Electron Device Meeting*, Washington, D.C. pp.319-322, Dec. 2002. - H. Shah, P. Shiu, B. Bell, M. Aldredge, N. Sopory, and J.A. Davis, “Repeater insertion and wire sizing optimization for throughput-centric VLSI Global Interconnect,”
*IEEE/ACM International Conference on Computer-Aided Design,*San Jose, CA, pp. 280-284, Nov. 2002. - R. Venkatesan, J.A. Davis, and J.D. Meindl, “A Complete Physical Model for Distributed RLC Interconnects — Transient Voltage, Time Delay and Crosstalk,”
*Proceeding of the IEEE/ACM Design Automation Conference (DAC)*, New Orleans, pp.763-766, June 2002. - R. Venkatesan, J.A. Davis and J.D. Meindl, “Time Delay, Crosstalk and Repeater Insertion Models for High Performance SoC’s,”
*Proceedings of the IEEE ASIC/SOC Conference*, Rochester, NY, pp. 404-408, Sept. 2002. - J. D. Meindl, R. Venkatesan, J. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. Bakir, T. Mule, P. Kohl, and K. Martin, “Interconnecting Device Opportunities for Gigascale Integration (GSI),”
*Technical Digest of International Meeting on Electron Device Meeting*, Washington, DC, pp. 525-258, December 2001. - A. Naeemi, J. A. Davis, and J. D. Meindl, “Analytical Models for Coupled Distributed RLC Lines with Ideal and Non-Ideal Return Paths,”
*Technical Digest of International Meeting on Electron Devices Meeting*, Washington, DC, pp. 689-692, December 2001. - J. W. Joyner, R. Venkatesan, P. Zarkesh-Ha, J.A. Davis, and J. D. Meindl, “Impact of Three-dimensional Architectures on Interconnects in Gigascale Integration,”
*IEEE Transactions on VLSI Systems*, vol. 9, no. 6, pp. 922-928, December 2001. - J.D. Meindl, Q. Chen, and J.A. Davis, “Limits on Silicon Nanoelectronics for Terascale Integration,”
*Science*, vol. 293, no. 5537, pp. 2044-2049, September, 2001. - R. Venkatesan, J. A. Davis, K. A. Bowman, and J. D. Meindl, “Optimal n-Tier Multilevel Interconnect Architectures for Gigascale Integration (GSI),”
*IEEE Transactions on VLSI Systems*, vol. 9, no. 6, pp. 899-912, December 2001. - J.A. Davis, R. Venkatesan, A. Kaloyeros, M. Bylansky, S.J. Souri, K. Banerjee, K.C. Saraswat, A. Rahman, R. Reif, and J.D. Meindl, “Interconnect Limits on Gigascale Integration (GSI) in the 21st Century,”
*Proceedings of the IEEE*, vol. 89, no. 3, pp. 305-324, March 2001. - J. D. Meindl and J.A. Davis, “The Fundamental Limit on Binary Switching Energy for Terascale Integration (TSI),”
*IEEE Journal of Solid-State Circuits*, vol. 35, no. 10, pp. 1515-1516, October 2000. - J. A. Davis and J. D. Meindl, “Compact Distributed RLC Interconnect Models Part I: Single Line Transient, Time Delay, and Overshoot Expressions,”
*IEEE Transactions on Electron Devices*, vol. 47, no. 11, pp. 2068-2077, November 2000. - J. A. Davis and J. D. Meindl, “Compact Distributed RLC Interconnect Models Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multilevel Networks,”
*IEEE Transactions on Electron Devices*, vol. 47, no. 11, pp. 2078-2087, November 2000. - Q. Chen, J. A. Davis, P. Zarkesh-Ha, and J. D. Meindl, “A Compact Physical via Blockage Model,”
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 8, no. 6, pp. 689-692, December 2000. - P. Zarkesh-Ha, J. A. Davis, and J. D. Meindl, “Prediction of Net-Length Distribution for Global Interconnects in a Heterogeneous System-on-a-Chip,”
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 8, no. 6, pp. 649-659, December 2000. - J. W. Joyner, P. Zarkesh-Ha, J. A. Davis, and J. Meindl, “Vertical Pitch Limitations on Performance Enhancement in Bonded Three-Dimensional Interconnect Architectures,”
*Proceedings of the International Workshop on System-Level Interconnect Prediction*, San Diego, CA, pp. 123-127, April 2000. - P. Zarkesh-Ha, J. A. Davis, W. Loh, and J. Meindl, “Prediction of Interconnect Fan-out Distribution Using Rent’s Rule,”
*Proceedings of the International Workshop on System-Level Interconnect Prediction*, San Diego, CA, pp. 107-112, April 2000. - J. W. Joyner, P. Zarkesh-Ha, J. A. Davis, and J. D. Meindl, “A Three-Dimensional Stochastic Wire-Length Distribution for Variable Separation of Strata,”
*Proceedings of the International Interconnect Technology Conference*, San Francisco, pp. 1126-1128, June 2000. - R. Venkatesan, J.A. Davis, K. Bowman, and J. Meindl, “Optimal Repeater Insertion for N-tier Multilevel Interconnect Architectures,”
*Proceedings of the International Interconnect Technology Conference*, San Francisco, CA, pp. 132-134, June 2000. - Q. Chen, J. A. Davis, P. Zarkesh-Ha, and J. D. Meindl, “A Novel Via Blockage Model and Its Implications,”
*Proceedings of the International Interconnect Technology Conference*, San Francisco, CA, pp. 15-17, June 2000. - R. Venkatesan, J.A. Davis, K. A. Bowman, and J. D. Meindl, “Minimum Power and Area N-Tier Multilevel Interconnect Architectures Using Optimal Repeater Insertion,”
*Proceedings of the International Symposium on Low Power Electronics and Design*, Rapallo/Portofino Coast, Italy, pp. 167-172, July 26-27, 2000. - J.A. Davis and J.D. Meindl, “Length, Scaling, and Material Dependence of Crosstalk between Distributed RC Interconnects,”
*Proceedings of the 1999 International Interconnect Technology Conference*, San Francisco, CA, pp. 227-229, May 1999. - J.A. Davis and J.D. Meindl, “Compact Distributed RLC Models for Multilevel Interconnect Networks,”
*1999 VLSI Symposium on Technology Digest of Technical Papers*, Kyoto, Japan, pp. 165-166, June 1999. - R. Venkatesan, J.A. Davis, and J.D. Meindl, “Performance Enhancement Through Optimal N-tier Multilevel Interconnect Architectures,”
*Proceedings of the 12th IEEE ASIC/SOC Conference*, Washington, DC, pp. 19-23, Sept. 1999. - P. Zaresh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, “On a Pin Versus Gate Relationship for Heterogeneous Systems: Heterogeneous Rent’s Rule,”
*Proceedings of the Custom Integrated Circuit Conference*, San Francisco, CA, pp. 93-96, May 1998. - J. A. Davis and J.D. Meindl, “Is Interconnect the Weak Link?”
*Circuits and Devices Magazine*, pp. 30-36, March 1998. - J.A. Davis, V.K De, and J.D. Meindl, “A Stochastic Wire Length Distribution for Gigascale Integration (GSI) Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation,”
*IEEE Transactions on Electron Devices*, vol. 45, no. 3, pp. 590-597, March 1998. - J.A. Davis, V.K. De, and J.D. Meindl, “A Stochastic Wire Length Distribution for Gigascale Integration (GSI) Part I: Derivation and Validation,”
*IEEE Transactions on Electron Devices*, vol. 45, no. 3, pp. 580-589, March 1998. - J.D. Meindl, V.K. De, D.S. Wills, J.C. Eble, X. Tang, J.A. Davis, B. Austin, and A.J. Bhavnagarwala, “Impact of Stochastic Dopant and Interconnect Distributions on Gigascale Integration,”
*Proceedings of the 1997 IEEE International Solid-State Circuits Conference*, San Francisco, CA, February 1997, pp. 232-233. - J.D. Meindl, J.A. Davis, X. Tang, J.C. Eble, A.J. Bhavnagarawala, and B. Austin, “Intrinsic Limits on Gigascale Integration due to Stochastic Dopant and Interconnect Placement,”
*Proceedings of the Government Microcircuit Application Conference (GOMAC ’97),*Las Vegas, NV, March 1997, pp. 305-308. - J. A. Davis, V. K. De, and J. D. Meindl, “A Stochastic Wire Length Distribution for Gigascale Integration,”
*Proceedings of the Custom Integrated Circuit Conference*, San Francisco, CA, pp.145-150, May 1997. - J.A. Davis and J.D. Meindl, “Interconnect Limits on Gigascale Integration (GSI),”
*Material Research Society Symposium Proceedings*, San Francisco, CA , vol. 473, pp. 293-302, 1997. - J. D. Meindl and J.A. Davis, “Interconnect Performance Limits of Gigascale Integration (GSI),”
*Materials Chemistry and Physics*, vol. 41, no. 3, pp. 161-166, August 1995. - J. D. Meindl, J.A. Davis, and G. Vish, “A New Metric for GSI,”
*Pico Frontier*, June 1, 1996. - 5. J. A. Davis, V. K. De, and J. D. Meindl, “Optimal Low Power Interconnect Networks,”
*Digest of Technical Papers of the 1996 Symposium on VLSI Technology*, Honolulu, HI, June 1996, pp. 78-79. - J. A. Davis, J. C. Eble, V. K. De, and J. D. Meindl, “A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI),”
*Material Research Society Symposium Proceedings*, San Francisco, CA, vol. 427, 1996, pp. 23-34. - J.C. Eble, V.K. De, J.A. Davis, and J.D. Meindl, “Optimal Multilevel Interconnect Technologies for Gigascale Integration (GSI),”
*1996 Proceedings of the 13*Santa Clara, CA, June 1996, pp. 40-45.^{th}Annual VLSI Multilevel Interconnection Conference (VMIC), - J. A. Davis, V. K. De, and J.D. Meindl, “A Priori Wiring Estimations and Optimal Multilevel Wiring Networks for Portable ULSI Systems,”
*Proceedings of 46*, Orlando, FL, May 1996, pp. 1002-1008.^{th}Electronic Components and Technology Conference - V.K. De, J.C. Eble, D.S. Wills, J.A. Davis, and J.D. Meindl, “A Generic System Simulator (GENESYS) for Microelectronics Technology and Applications,”
*Proceedings of the Government Microcircuit Application Conference (GOMAC’96),*Orlando, FL, March 1996, pp. 439-442.