Dr. Jeffrey A. Davis Associate Professor School of Electrical Engineering February 2014

Dr. Jeffrey A. Davis Associate Professor School of Electrical Engineering February 2014

Dr. Jeffrey A. Davis
Associate Professor
School of Electrical Engineering
February 2014

I. Earned Degrees

B.E.E.  1993     Ga. Tech     Electrical Engineering
M.S.E.E. 1997     Ga. Tech     Electrical Engineering
Ph.D. 1999     Ga. Tech     Electrical and Computer Engineering

II. Employment

Associate Professor – 6/06-present
Georgia Institute of Technology
School of Electrical & Computer Engineering
(Atlanta, Georgia)

Assistant Professor – >8/99 – 6/06
Georgia Institute of Technology
School of Electrical & Computer Engineering
(Atlanta, Georgia)

Graduate Research Assistant – 1/94-7/99
Georgia Institute of Technology
School of Electrical & Computer Engineering
(Atlanta, Georgia)

Engineering Intern – 6/92-9/92
Lawrence Livermore National Laboratory (Livermore, CA)

Engineering Intern – 6/91-9/91
International Business Corporation (Lexington, KY )

Resident Housing Assistant – 9/91- 6/93
Georgia Institute of Technology Housing Department   (Atlanta, GA)

III. Teaching
A. Individual Student Guidance
Ph.D. Students Supervised
Graduated Ph.D. Students
1.Raguraman Venkatesan
Began advising: Spring 2001  (co-advised with Prof. James Meindl)
Preliminary exam passed: Spring 1999
Proposal exam passed: Spring 2002
Graduated: Spring 2003
Research Topic:  Optimal Multilevel Interconnect Architectures for Gigascale Integration (GSI)
Employment: Intel Corporation

2.Vinita Deodhar
Began advising: Fall 2001
Preliminary exam passed: Fall 2001
Proposal exam passed: Spring 2005
Graduated: Summer 2006
Research Topic: Throughput-Centric Wave-Pipelined Interconnect Circuits for Gigascale Integration
Employment: Intel Corporation and now Analog Devices

3.Ajay Joshi
Began advising: Fall 2001
Preliminary exam passed: Fall 2001
Proposal exam passed: Fall 2005
Graduated: Summer 2006
Research Topic: Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI)
Employment: Post-doctorial student at M.I.T. and now on faculty at Boston University

4.Pranav Anbalagan
Began advising: Fall 2000
Preliminary exam passed: Spring 2001
Proposal exam passed: Fall 2005
Graduated: Spring 2007
Research Topic: Limitations and Opportunities for Wire Length Prediction in Gigascale Integration
Employment: Post-doctorial student at Georgia Tech and now with a recent startup company, Solexel

5.Deepak Sekar
Began advising: Spring 2002 (co-advised with Prof. James Meindl)
Preliminary exam passed: Spring 2002
Proposal exam passed: Fall 2007
Graduated: Fall 2008
Research Topic: Optimal Signal, Power, Clock and Thermal Interconnect Networks for High-Performance 2D and 3D Integrated Circuits.
Employment: SanDisk Corporation

6.Gerald Lopez
Began advising: Spring 2002 (co-advised with Prof. James Meindl)
Preliminary exam passed: Fall 2002
Proposal exam passed: Spring 2009
Graduated: Fall 2009
Thesis Title: The Impact of Interconnect Process Variations and Size Effects for Gigascale Integration
Employment: Interviewing

Master’s Student Guidance
Graduated Master’s Students

1.Harshit Shaw
Began advising: Fall 2000
Graduated:  Spring 2002
Preliminary exam passed: Spring 2001
Research Topic: Opportunities and Limitations of High-throughput Global Interconnect Networks
2.Mamie Aldridge
Began advising:  Fall 2002
Graduated:  Spring 2004
Research Topic:  VLSI Global Power Distribution Networks
3.Alex Talpasanu
Began Advising: Fall 2003
Graduated: Fall 2004
Research Topic: Interconnect Modeling of Custom Bus Architectures
4.Heather Luman
Began advising: Fall 2002
Graduated: Spring 2005
Research Topic: On-chip Inductance Insertion for High Performance Clock Distribution Networks
5. Bobby Kim
Began advising: Fall 2007
Graduated: Fall 2007
Research Topic: Low-Static Power Interconnect Circuits

Undergraduate Student Guidance
1. Mamie Aldridge (Summer Undergraduate Research in Engineering (SURE) Program)
Advised: Summer 2000
Project Title: The Impact of On-chip Interconnect Communication Networks on Reducing Wiring Demand for Gigascale Integration
2. James Freedman (UROP)
Advised: Spring 2000
Project title:  Interconnect Prediction for a Interconnect-centric VLSI Design Flow
3. Brian Bell (UROP)
Advised: Spring 2000-Fall 2002
Project title:  Maximizing Bandwidth per Unit Area for On-chip Networks
4. Chris Shoukry (UROP)
Advised: Spring 2000–Fall 2002
Project title:  Quasi-Optimal High-Speed Repeater Networks for ULSI
5. Tim Cooper (UROP)
Advised: Spring 2000-Summer 2003
Project title:  Quasi-Optimal High-Speed Repeater Networks for ULSI
6. Jonathan James (UROP)
Advised: Spring 2000
Project title: Interconnect Complexity Metrics for the Future of Computing
7. Vaibhav Jain (UROP)
Advised: Fall 2000
Project title: Cache Area Models
8. Garth Milford (UROP and special problems)
Advised: Spring 2000-Fall 2002
Project title: Computer Engineering Education for K-12
9. Melissa Gravely (UROP and special problems)
Advised: Spring 2000
Project title: Computer Engineering Education for K-12
10. Arica Carter (UROP and special problems)
Advised: Spring 2000
Project title: Computer Engineering Education for K-12
11. Kevin Delk (UROP and special problems)
Advised: Spring 2000
Project title: High-Speed Interconnect Design
12. Jeet Shaw (UROP and special problems)
Advised: Spring 2001
Project title: Computer Engineering Education for K-12
13. Sekou Remy (UROP and SURE Program)
Advised: Spring 2000-Summer 2002
Project title: Statistical Properties of Logic Netlists
14. Kerron Miles (UROP and special problems)
Advised: Summer 2002-Summer 2003
Project title: Computer Engineering Education for K-12
15. Saunvit Pandya (UROP)
Advised: Spring 2003-Summer 2004
Project Title: Impact of Vias on Throughput-centric VLSI Wire Design
16. Nirav Bodiwali (UROP)
Advised: Spring 2003-Fall 2003
Project Title: VLSI Interconnect Statistical Extraction Methods
17. Reshma Parekh (PURA)
Advised:  Spring 2003-Fall 2003
Project Title: Interconnect Limits for Current VLSI Designs
18. Aziza Rahman (PURA)
Advised: Spring 2004-Spring 2005
Project Title: Extraction of Wiring Statistics Using SKILL Code
19. Ifiok Udowana (PURA)
Advised: Spring 2004-Fall 2004
Project Title: Efficient HSPICE Models of VLSI Global Wires

20.Mark Youngblood (PURA and Undergraduate Research Option)
Advised: Spring 2006-2007
Project Title: Low-Threshold Devices in Wave-Pipelined Circuits
Undergraduate Thesis Research Option: Competed Spring 2007
21. David Esiobu (UROP CLASS and PURA)
Advised: Spring 2006-Fall 2007
Project Title: Bi-Directional Wave-Pipelined Circuits for Global Bus Structures

22.Name: Joseph Roberson (UROP CLASS)
Advised: Fall 2007-Spring 2008
Project Title: Low-power VLSI Circuits using Charge Recycled Repeaters

23.Name: Nathan Jones (UROP CLASS)
Advised: Spring 2008 – Spring 2009
Project Title: Anomalous Dielectric Constant Increases in Nanocomposite Materials for High Energy Density Storage.

24.Name: Estee E. Amana (UROP CLASS)
Advised: Spring 2008-Fall 2008
Project Title: Low Power Interconnect Circuits

25.Name: Daniel Deller (UROP CLASS)
Advised: Summer 2008-Fall 2008
Project Title:  The Role of Entropy in Simulated Annealing (SA) Algorithms

26.Name: Matthew Lane (UROP CLASS)
Advised: Fall 2008 – Summer 2009
Project Title: Theories on Increasing the Capacitance and Dielectric Constant in a Dielectric

27.Name: Sarah El-Helw (Undergraduate Research Option)
Advised: Spring 2008 – Spring 2010
Project Title: Optimization of Wave-pipelined Multiplex Encoded (WPE) VLSI Circuits

B. Other Teaching Activities

New Course Development
ECE4823 Computational Methods in Electrical Engineering
This class is being developed to enhance undergraduate education in the area of computational methods, which include finite difference and finite element methods, to solve ordinary and partial differential equations.  The unique aspect of the course is that the applications are focused on physical phenomenon that is specifically observed in electrical engineering. As a special topics course, the effective teaching evaluations have been 4.8 for the first teaching and a perfect 5.0 in the second.

IV. Scholarly Accomplishments

A.Published Books And Parts Of Books
1.J.A. Davis and J.D. Meindl, Eds., Interconnect Technology and Design for Gigascale Integration. Boston: Kluwer Academic Publishers, 2003.
2.J.A. Davis and J.D. Meindl, Eds., Interconnect Technology and Design for Gigascale Integration. China Machine Press, 2010. [Chinese Translation]
3.J.A. Davis, A. Naeemi, and J. Meindl, “Distributed RC and RLC Transient Models,” Interconnect Technology and Design for Gigascale Integration. Boston: Kluwer Academic Publishers, pp. 111-158, 2003.
4.J.A. Davis, R. Venkatesan, and J. Meindl, “Stochastic Multilevel Interconnect Modeling and Optimization,” Interconnect Technology and Design for Gigascale Integration. Boston: Kluwer Academic Publishers, pp. 219-262, 2003.

B.Refereed Publications
Refereed Journal Papers
1.J. D. Meindl and J.A. Davis, “Interconnect Performance Limits of Gigascale Integration (GSI),” Materials Chemistry and Physics, vol. 41, no. 3, pp. 161-166, August 1995.
2.J. D. Meindl, J.A. Davis, and G. Vish, “A New Metric for GSI,” Pico Frontier, June 1, 1996.
3.J.A. Davis, V.K. De, and J.D. Meindl, “A Stochastic Wire Length Distribution for Gigascale Integration (GSI) Part I: Derivation and Validation,” IEEE Transactions on Electron Devices, vol. 45, no. 3, pp. 580-589, March 1998.
4.J.A. Davis, V.K De, and J.D. Meindl, “A Stochastic Wire Length Distribution for Gigascale Integration (GSI) Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation,” IEEE Transactions on Electron Devices, vol. 45, no. 3, pp. 590-597, March 1998.
5.J. A. Davis and J.D. Meindl, “Is Interconnect the Weak Link?” Circuits and Devices Magazine, pp. 30-36, March 1998.
6.J. D. Meindl and J.A. Davis, “The Fundamental Limit on Binary Switching Energy for Terascale Integration (TSI),” IEEE Journal of Solid-State Circuits, vol. 35, no. 10, pp. 1515-1516, October 2000.
7.J. A. Davis and J. D. Meindl, “Compact Distributed RLC Interconnect Models Part I: Single Line Transient, Time Delay, and Overshoot Expressions,” IEEE Transactions on Electron Devices, vol. 47, no. 11, pp. 2068-2077, November 2000.
8.J. A. Davis and J. D. Meindl, “Compact Distributed RLC Interconnect Models Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multilevel Networks,” IEEE Transactions on Electron Devices, vol. 47, no. 11, pp. 2078-2087, November 2000.
9.Q. Chen, J. A. Davis, P. Zarkesh-Ha, and J. D. Meindl, “A Compact Physical via Blockage Model,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 6, pp. 689-692, December 2000.
10.P. Zarkesh-Ha, J. A. Davis, and J. D. Meindl, “Prediction of Net-Length Distribution for Global Interconnects in a Heterogeneous System-on-a-Chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 6, pp. 649-659, December 2000.
11.J.A. Davis, R. Venkatesan, A. Kaloyeros, M. Bylansky, S.J. Souri, K. Banerjee, K.C. Saraswat, A. Rahman, R. Reif, and J.D. Meindl, “Interconnect Limits on Gigascale Integration (GSI) in the 21st Century,” Proceedings of the IEEE, vol. 89, no. 3, pp. 305-324, March 2001.
12.J.D. Meindl, Q. Chen, and J.A. Davis, “Limits on Silicon Nanoelectronics for Terascale Integration,” Science, vol. 293, no. 5537, pp. 2044-2049, September, 2001.
13.R. Venkatesan, J. A. Davis, K. A. Bowman, and J. D. Meindl, “Optimal n-Tier Multilevel Interconnect Architectures for Gigascale Integration (GSI),” IEEE Transactions on VLSI Systems, vol. 9, no. 6, pp. 899-912, December 2001.
14.J. W. Joyner, R. Venkatesan, P. Zarkesh-Ha, J.A. Davis, and J. D. Meindl, “Impact of Three-dimensional Architectures on Interconnects in Gigascale Integration,” IEEE Transactions on VLSI Systems, vol. 9, no. 6, pp. 922-928, December 2001.
15.R. Venkatesan, J.A. Davis, and J.D. Meindl, “Compact Distributed RLC Interconnect Models – Part III: Transients in Single and Coupled Lines with Capacitive Load Termination,” IEEE Transactions on Electron Devices, vol. 50, no. 4, pp. 1081-1093, April 2003.
16.R. Venkatesan, J.A. Davis, and J.D. Meindl, “Compact Distributed RLC Interconnect Models – Part IV: Unified Models for Time Delay, Crosstalk and Repeater Insertion,” IEEE Transactions on Electron Devices, vol. 50, no. 4, pp. 1094-1102, April 2003.
17.A. Naeemi, J. A. Davis, and J. D. Meindl, “Analysis and Optimization of Co-planar RLC Lines for GSI global interconnection,” IEEE Trans. Electron. Devices, vol. 51, pp. 985-995, June 2004.
18.A. Naeemi, J. A. Davis, and J. D. Meindl, “Compact physical models for multilevel interconnect crosstalk in GSI,” IEEE Trans. Electron. Devices, vol. 51, no. 11, pp. 1902-1912, November 2004.
19.V. Deodhar and J.A. Davis, “Optimization of Throughput Performance for Low Power VLSI Interconnects,” IEEE Transactions on VLSI Systems, vol. 13, no. 3, pp. 308-318, March 2005.
20.A. Joshi and J.A. Davis, “Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI),” IEEE Transactions on VLSI Systems, vol. 13, no. 8, pp. 899-910, August 2005.
21.H. Yamamoto and J.A. Davis, “Decreased Effectiveness on On-chip Decoupling Capacitance in High Frequency Operation,” IEEE Transactions on VLSI Systems, vol. 15, no. 6, pp. 649-659, June 2007.
22.A. Joshi, G. Lopez, and J.A. Davis, “Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing,” IEEE Transactions on VLSI Systems, vol. 15, no. 9, pp. 990-1002, September 2007.
23.D. Sekar, B. Dang, J.A. Davis, J.D. Meindl, “Electromigration Resistant Power Delivery Systems,” IEEE Electron Device Letters, Vol. 28, no. 8, pp. 767-769, August 2007.
24.V. Deodhar and J.A. Davis, “Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects,” IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Application, vol. 55, no. 4, pp.1023-30, May 2008.
25.G. Lopez, J. Davis, and J. Meindl, “A New Closed-Form Effective Resistivity Model: Derivation, Verification and ITRS Impact”, Submitted to the IEEE Transaction on Electron Devices during March 2011.
26.J. Davis, D. Brown, W. Henderson, “Fractal Electrode Formation in Metal-Insulator Composites Near the Percolation Threshold,” IEEE Transactions on Nanotechnology, vol. 12, no. 5, pp. 725-733, Sept. 2013.

Refereed Conference Publications
1. V.K. De, J.C. Eble, D.S. Wills, J.A. Davis, and J.D. Meindl, “A Generic System Simulator (GENESYS) for Microelectronics Technology and Applications,” Proceedings of the Government Microcircuit Application Conference (GOMAC’96), Orlando, FL, March 1996, pp. 439-442.
2. J. A. Davis, V. K. De, and J.D. Meindl, “A Priori Wiring Estimations and Optimal Multilevel Wiring Networks for Portable ULSI Systems,” Proceedings of 46th Electronic Components and Technology Conference, Orlando, FL, May 1996, pp. 1002-1008.
3. J.C. Eble, V.K. De, J.A. Davis, and J.D. Meindl, “Optimal Multilevel Interconnect Technologies for Gigascale Integration (GSI),” 1996 Proceedings of the 13th Annual VLSI Multilevel Interconnection Conference (VMIC), Santa Clara, CA, June 1996, pp. 40-45.
4. J. A. Davis, J. C. Eble, V. K. De, and J. D. Meindl, “A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI),” Material Research Society Symposium Proceedings, San Francisco, CA, vol. 427, 1996, pp. 23-34.
5. J. A. Davis, V. K. De, and J. D. Meindl, “Optimal Low Power Interconnect Networks,” Digest of Technical Papers of the 1996 Symposium on VLSI Technology, Honolulu, HI, June 1996, pp. 78-79.
6. J.D. Meindl, V.K. De, D.S. Wills, J.C. Eble, X. Tang, J.A. Davis, B. Austin, and A.J. Bhavnagarwala, “Impact of Stochastic Dopant and Interconnect Distributions on Gigascale Integration,” Proceedings of the 1997 IEEE International Solid-State Circuits Conference, San Francisco, CA, February 1997, pp. 232-233.
7. J.D. Meindl, J.A. Davis, X. Tang, J.C. Eble, A.J. Bhavnagarawala, and B. Austin, “Intrinsic Limits on Gigascale Integration due to Stochastic Dopant and Interconnect Placement,” Proceedings of the Government Microcircuit Application Conference (GOMAC ’97), Las Vegas, NV, March 1997, pp. 305-308.
8. J. A. Davis, V. K. De, and J. D. Meindl, “A Stochastic Wire Length Distribution for Gigascale Integration,” Proceedings of the Custom Integrated Circuit Conference, San Francisco, CA, pp.145-150, May 1997.
9. J.A. Davis and J.D. Meindl, “Interconnect Limits on Gigascale Integration (GSI),” Material Research Society Symposium Proceedings, San Francisco, CA , vol. 473, pp. 293-302, 1997.
10. P. Zaresh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, “On a Pin Versus Gate Relationship for Heterogeneous Systems: Heterogeneous Rent’s Rule,” Proceedings of the Custom Integrated Circuit Conference, San Francisco, CA, pp. 93-96, May 1998.
11. J.A. Davis and J.D. Meindl, “Length, Scaling, and Material Dependence of Crosstalk between Distributed RC Interconnects,” Proceedings of the 1999 International Interconnect Technology Conference, San Francisco, CA, pp. 227-229, May 1999.
12. J.A. Davis and J.D. Meindl, “Compact Distributed RLC Models for Multilevel Interconnect Networks,” 1999 VLSI Symposium on Technology Digest of Technical Papers, Kyoto, Japan, pp. 165-166, June 1999.
13. R. Venkatesan, J.A. Davis, and J.D. Meindl, “Performance Enhancement Through Optimal N-tier Multilevel Interconnect Architectures,” Proceedings of the 12th IEEE ASIC/SOC Conference, Washington, DC, pp. 19-23, Sept. 1999.
14. J. W. Joyner, P. Zarkesh-Ha, J. A. Davis, and J. Meindl, “Vertical Pitch Limitations on Performance Enhancement in Bonded Three-Dimensional Interconnect Architectures,” Proceedings of the International Workshop on System-Level Interconnect Prediction, San Diego, CA, pp. 123-127, April 2000.
15. P. Zarkesh-Ha, J. A. Davis, W.  Loh, and J. Meindl, “Prediction of Interconnect Fan-out Distribution Using Rent’s Rule,” Proceedings of the International Workshop on System-Level Interconnect Prediction, San Diego, CA, pp. 107-112, April 2000.
16. J. W. Joyner, P. Zarkesh-Ha, J. A. Davis, and J. D. Meindl, “A Three-Dimensional Stochastic Wire-Length Distribution for Variable Separation of Strata,” Proceedings of the International Interconnect Technology Conference, San Francisco, pp. 1126-1128, June 2000.
17. R. Venkatesan, J.A. Davis, K. Bowman, and J. Meindl, “Optimal Repeater Insertion for N-tier Multilevel Interconnect Architectures,” Proceedings of the International Interconnect Technology Conference, San Francisco, CA, pp. 132-134, June 2000.
18. Q. Chen, J. A. Davis, P. Zarkesh-Ha, and J. D. Meindl, “A Novel Via Blockage Model and Its Implications,” Proceedings of the International Interconnect Technology Conference, San Francisco, CA, pp. 15-17, June 2000.
19. R. Venkatesan, J.A. Davis, K. A. Bowman, and J. D. Meindl, “Minimum Power and Area N-Tier Multilevel Interconnect Architectures Using Optimal Repeater Insertion,” Proceedings of the International Symposium on Low Power Electronics and Design, Rapallo/Portofino Coast, Italy, pp. 167-172, July 26-27, 2000.
20. J. D. Meindl, R. Venkatesan, J. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. Bakir, T. Mule, P. Kohl, and K. Martin, “Interconnecting Device Opportunities for Gigascale Integration (GSI),” Technical Digest of International Meeting on Electron Device Meeting, Washington, DC, pp. 525-258, December 2001.
21. A. Naeemi, J. A. Davis, and J. D. Meindl, “Analytical Models for Coupled Distributed RLC Lines with Ideal and Non-Ideal Return Paths,” Technical Digest of International Meeting on Electron Devices Meeting, Washington, DC, pp. 689-692, December 2001.
22. R. Venkatesan, J.A. Davis, and J.D. Meindl, “A Complete Physical Model for Distributed RLC Interconnects — Transient Voltage, Time Delay and Crosstalk,” Proceeding of the IEEE/ACM Design Automation Conference (DAC), New Orleans, pp.763-766, June 2002.
23. R. Venkatesan, J.A. Davis and J.D. Meindl, “Time Delay, Crosstalk and Repeater Insertion Models for High Performance SoC’s,” Proceedings of the IEEE ASIC/SOC Conference, Rochester, NY, pp. 404-408, Sept. 2002.
24. H. Shah, P. Shiu, B. Bell, M. Aldredge, N. Sopory, and J.A. Davis, “Repeater insertion and wire sizing optimization for throughput-centric VLSI Global Interconnect,” IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 280-284, Nov. 2002.
25.A. Naeemi, J.A. Davis, and J.D. Meindl, “Optimal Global Interconnect Devices for GSI,” Technical Digest of International Electron Device Meeting, Washington, D.C. pp.319-322, Dec. 2002.
26. P. Anbalagan and J.A. Davis, “Maximum Multiplicity Distributions (MMD),” International Workshop on System Level Interconnect Prediction, Monterey, CA, pp. 107-113, April 2003.
27.A. Talpasanu, G. Milford, K. S. A. Miles, and J.A. Davis “Computer Educational Datapath (CED): Basic Computer Design for K-12 Education,” IEEE International Conference on Information Technology (ITCC), Las Vegas, Nevada, pp. 86-90, April 2003.
28.J.W. Joyner, R. Venkatesan, J.A. Davis, J.D. Meindl, “The limits of system improvements through liquid diagonal routing of interconnects,” Proceedings of the IEEE 2003 International Interconnect Technology Conference, June 2003, pp.227-229.
29.V. Deodhar and J.A. Davis, “Voltage Scaling and Repeater Insertion for High-Throughput Low-Power Interconnect Networks,” Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, pp.  349-352, June 2003.
30.R. Venkatesan, J.A. Davis, and  J.D. Meindl, “Optimal Multilevel Interconnect Architecture Aspect Ratios for GSOCs,”  Proceedings of the 2003 IEEE SOC Conference, Rochester, NY, pp. 17-20, September 2003.
31.A. Naeemi, J.A. Davis, J.D. Meindl, “Compact Physical Models for Multielvel Interconnect Crosstalk in Gigascale SoC,” Proceedings of the IEEE International SoC Conference, Rochester, NY, pp. 199-202, September 2003.
32.A. Joshi and J.A. Davis, “A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI)” 2004 IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP), Paris, France, pp. 64-46, February 2004.
33.P. Anbalagan and J.A. Davis, “Maximum Multiplicity Distribution for Length Prediction Driven Placement,” 17th International Conference on VLSI Design, Mumbai, India, pp. 981-986, April 2004.
34. H. Luman and J.A. Davis, “Inductance Enhancement in Global Clock Distribution Networks,” 2004 IEEE International Interconnect Technology Conference (IITC), San Francisco, CA, pp. 119-122, June 2004.
35.K.K. Ryu, A. Talpasanu, V. Mooney, and J.A. Davis, “Interconnect Delay Aware RTL Verilog Bus Architecture Generation for an SoC,” Asia-Pacific Conference on Advanced Systems Integrated Circuits (AP-ASIC 2004), Japan, pp.176-179, August 2004.
36.V. Deodhar and J. Davis, “Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits,” IEEE International Symposium on Quality Electronic Design (ISQED), pp. 592-596, March 2005.
37.V. Deodhar and J. Davis, “Designing for Signal Integrity in Wave-Pipelined SoC Global Interconnects,” Proceedings of the IEEE System-on-Chip Conference (SOCC), pp. 207-210, September 2005.
38.A. Joshi and J. Davis, “Gigascale ASIC/SOC Design Using Wave-Pipelined Multiplexed (WPM) Routing,” Proceedings of the IEEE System-on-Chip Conference (SOCC), pp. 137-142, September 2005.
39.J.A. Davis, V. Deodhar, and A. Joshi, “The Impact of Wave Pipelining on Future Interconnect Technologies,” Advanced Metallization Conference 2005, pp. 17-23, October, 2005.
40.A. Joshi, V. Deodhar, and J. Davis, “Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing,” IEEE VLSI Design Conference, pp. 773-776, January 2006.
41.D.C. Sekar, R. Venkatesan, K.A. Bowman, A. Joshi, J.A. Davis, and J.D. Meindl, “Optimal Repeaters for Sub-50nm Interconnect Networks,” Proceedings of the IEEE 2006 International Interconnect Technology Conference, pp. 3-7, June 2006.
42.P. Anbalagan and J.A. Davis, “A Priori Prediction of Tightly Clustered Connections Based on Heuristic Classification Trees,” Proceedings of the International Workshop on System Level Interconnect Prediction (SLIP), pp. 9-15, April 2006.
43.G. Lopez, R. Murali, R. Sarvari, K. Bowman, J. Davis, and J. Meindl, “The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors,” Proceedings of the IEEE 2007 International Interconnect Technology Conference, pp. 40-42, June 2007.
44.D. Sekar,  A. Naeemi, R. Sarvari, J. Davis, and J. Meindl, “Intsim: A CAD Tool for Optimization of Multilevel Interconnect Networks,” Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 560-567, November 2007.
45.M. Usselman, J. Davis, and J. Rosen, “Diversifying Participation in FIRST LEGO League,” 2008 American Society for Engineering Education (ASEE) Conference Proceedings, pp. 750,  2008.
46.G. Lopez, J. Davis, and J. Meindl, “A New Physical Model and Experimental Measurements of Copper Interconnect Resistivity Considering Size Effects and Line-Edge Roughness (LER),” Proceedings of the IEEE 2009 International Interconnect Technology Conference (IITC), pp. 231-234, June 2009.

C.Other Publications
1.J.A. Davis, “Guest Editorial for Special Issue on System Level Interconnect Prediction (SLIP)”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 4, pp. 337-338, April 2004.
2.J. Davis, V. Deodhar, and A. Joshi, “The Impact of Wave Pipelining on Future Interconnect Technologies,” invited paper, Advanced Metallization Conference (AMC), Colorado Springs, Colorado, September 2005.

D. Presentations
1.J.A. Davis, R. Venkatesan, K. Bowman, and J.D. Meindl, “Gigascale Integration (GSI) Interconnect Limits and N-Tier Multilevel Interconnect Architectural Solutions,” Proceedings of the International Workshop on System-Level Interconnect Prediction, San Diego, CA, pp. 147-148, April 8-9, 2000.
2.J.A. Davis, A. Naeemi, and V. Deodhar, “Compact Models for VLSI Interconnects”, Tutorial Session at the International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 22, 2004.

V. Service
A. Professional Contributions
Professional Society Activities
Committee Member of the 2001 International Technology Roadmap for Semiconductor Technical Working Group (TWG) for Design
IEEE Member 2001-2005
IEEE Senior Member 2005-present

Conference and Workshop Committees
1.Co-Program Chair 2001 and General Chair for 2002 System Level Interconnect Prediction (SLIP) Workshop
2.Review Committee Member for IEEE Symposium on Circuits and Systems 2004 (5 papers)

Editorial and Reviewer Activities
Reviewer for IEEE Transactions on VLSI Systems (17 papers) 2000-present
Reviewer for IEEE International Symposium on Circuits and Systems (6 papers) 2001-present
Reviewer for International Workshop on SLIP  (17 papers) 2000-present
Reviewer for IEEE Proceedings (1 paper total) 2001-present
Reviewer for IEEE Transactions on CAD (2 papers total) 2003-present
Reviewer for IEEE Transactions on Nanotechnology (1 paper total) 2003-present
Guest Editor for Special Section of the IEEE Transactions on VLSI Systems on System-Level Interconnect Prediction Issue (April 2004).

Campus Contributions
Service on School Committees
ECE Student Faculty Committee (ECESFC) Member (1999-2009) and Chair (2000-2008)
As chair, the ECESFC help to organize a set of yearly activities that include: ECE Family Day, ECE Student Awards, TIG Week, Freshman-Sophomore Class meetings, Take-A-Professor to lunch, Undergraduate Research Opportunity Program (UROP) Paper Competition, and outreach through FIRST LEGO League.
COE representative on Institute Undergraduate Curriculum Committee (IUCC) (2002-2005)
COE representative on the Campus Undergraduate Research Committee (2004-2006)
COE representative on the Institute Student Integrity Committee (2011- 2012)
COE chair of Institute Academic Integrity Committee (2013)
ECE representative on the Academic Senate (2012-2014)

C. Other Contributions
1.FIRST LEGO League State Competition Coordinator (2009-present)

In coordination with the Center for Education Integrating Science, Mathematics, and Computing (CEISMC), Jeff Davis helps to coordinate the State Level Competition for FIRST LEGO League in the state of Georgia. This tournament hosts the top 48 teams in the state (out of approximately 500 that competed throughout the state in 2012).  In this endeavor, he incorporates over 80 Georgia Tech student volunteers to help run the competition in the Student Center at Georgia Tech.  Tom Collins is the Judges Coordinator for the event, and he leads a team of 30 judges to determine the overall winners of the event.
2.Thinkbig Advisor (2009-2012)

In this activity, Jeff Davis met 1-2 times per week with a group of about 25 students who lived together in Georgia Tech Housing.  Jeff Davis’ goal was to bring a sense of community to their group, and encourage them to participate in outreach projects in the state of Georgia.  In addition, this community helped to break down the barriers between students and faculty at Georgia Tech, and it facilitated communication and discussion between faculty and students outside the classroom.

3.FIRST LEGO League Tournament Partner for the State of Georgia (2001-2008)

As tournament partner, Jeff Davis established the FIRST LEGO Robotic Competition in the state of Georgia.  In November 2003 over 260 elementary and middle school students participated in this event. On January 15th, 2005 over 420 elementary and middle school children participated in this event at Georgia Tech Campus Recreational Center (CRC). On January 20th, 2007 over 400 elementary and middle school children participated in this event at the Georgia Tech Student Center.

4.NSF Fast Student Mentor (2002-2008)
5.Intel Undergraduate Research Advisor (2003-2006)

VI. Honors and Awards
1.Georgia Institute of Technology, School of Electrical and Computer Engineering’s 1993 Faculty Award.
This award was received as a student in the ECE department for dedication and service to the school.
2.Georgia Institute of Technology President’s Fellow, 1994-1997
3.Best Student Paper Award of the 1999 International Interconnect Technology Conference
4.NSF CAREER Award (January 2001)
5.School of Electrical and Computer Engineering Outstanding Junior Faculty Award (April 2003)
6.2004-2005 Class of 1940 W. Roane Beard Outstanding Teacher Award
“In recognition of his excellence in teaching, inspiration to students, and intellectual integrity”
7.2006 Education Partnership Award
“In recognition of his collaborative efforts in support of K-12 education”
8.2006-2007 Outreach Award School of Electrical and Computer Engineering
9.2007 HKN Richard M. Bass Outstanding Teaching Award
10.2009 S.C. Sun Best Student Paper Award
This was awarded for one of Jeff Davis’ Ph.D. students in his paper entitled “A New Physical Model and Experimental Measurements of Copper Interconnect Resistivity Considering Size Effects and Line-Edge Roughness (LER)” which was presented at the 2009 International Interconnect Technology Conference.
11.2010 Hesburgh Award Teaching Fellow
12. 2010-2011 Class of 1934 Course Survey Teaching Effectiveness Award
13.2012-2013 Outreach Award School of Electrical and Computer Engineering
14. 2012-2013 Class of 1934 Course Survey Teaching Effectiveness Award

“Faculty awarded this honor had a response rate of at least 85 percent to the Course-Instructor Opinion Survey and had teaching effectiveness scores of 4.8 in classes that were at least 40 students in size or scores of 4.9 in classes that were at least 15 students in size.”